Intermedio > Circuitos integrados > Logica secuencial VHDL

Logica secuencial VHDL

Objetivos

  1. Poder desarrollar circuitos digitales usando la herramienta de Edición de texto en Lógica secuencial mediante el ISE de Xilinx.
  2. Poder simular circuitos digitales usando el software de simulación
  3. Analizar he interpretar los resultados de la simulación.

Procedimiento

PRIMERA PARTE: Maquina de estado tipo MOORE

Analizar el código, hacer su simulación y dibujar las máquinas de estado del funcionamiento.

  • ENTITY Diagrama_estados is
  • PORT ( rst : in STD_LOGIC;
  • CLK : in STD_LOGIC;
  • a : out STD_LOGIC;
  • b : out STD_LOGIC;
  • state: out STD_lOGIC_VECTOR(3 downto 0)
  • );
  • end Diagrama_estados;
  • architecture synth of Diagrama_estados is
  • SIGNAL pstate : std_logic_vector(3 downto 0);
  • SIGNAL n_state: std_logic_vector (3 downto 0);
  • BEGIN
  • --maquina de estados
  • PROCESS (clk, rst)
  • BEGIN
  • IF rst = '1' then
  • pstate <= "0000";
  • ELSIF clk = '1' AND clk'event then
  • pstate <= n_state;
  • END IF;
  • END PROCESS;
  • state <= pstate;
  • n_state <= "0001" when (pstate = "0000") ELSE
  • "0010" when (pstate = "0001") ELSE
  • "0011" when (pstate = "0010") ELSE
  • "0100" when (pstate = "0011") ELSE
  • "0101" when (pstate = "0100") ELSE
  • "0011" when (pstate = "0101") ELSE
  • "0111" when (pstate = "0011") ELSE
  • "1000" when (pstate = "0111") ELSE
  • "1001" when (pstate = "1000") ELSE
  • "0000";
  • a <='1' when pstate = "0000" else --0
  • '0' when pstate="0001" ELSE -1
  • '0' when pstate="0010" ELSE -2
  • '1' when pstate="0011" ELSE -3
  • '1' when pstate="0100" ELSE -4
  • '1' when pstate="0101" ELSE -5
  • '1' when pstate="0110" ELSE -6
  • '1' when pstate="0111" ELSE -7
  • '1' when pstate="1000" ELSE -8
  • '1' when pstate="1001" ELSE -9
  • '0';
  • b <='1' when pstate = "0000" else --0
  • '1' when pstate="0001" ELSE -1
  • '1' when pstate="0010" ELSE -2
  • '1' when pstate="0011" ELSE -3
  • '1' when pstate="0100" ELSE -4
  • '0' when pstate="0101" ELSE -5
  • '0' when pstate="0110" ELSE -6
  • '1' when pstate="0111" ELSE -7
  • '1' when pstate="1000" ELSE -8
  • '1' when pstate="1001" ELSE -9
  • '0';
  • END synth;

    1. LIBRARY ieee;
    2. USE ieee.std_logic_1164.ALL;
    3. ENTITY test_bench13 IS
    4. END test_bench13;
    6. ARCHITECTURE behavior OF test_bench13 IS
    8. COMPONENT implementacion13
    9. PORT(
    10. rst : IN std_logic;
    11. clk : IN std_logic;
    12. a : OUT std_logic;
    13. b : OUT std_logic;
    14. state: OUT std_logic_vector(3 downto 0)
    15. );
    16. END COMPONENT;
    18. --Inputs
    19. SIGNAL rst : std_logic := '0';
    20. SIGNAL clk : std_logic := '0';
    22. --Outputs
    23. SIGNAL a : std_logic;
    24. SIGNAL b : std_logic;
    25. SIGNAL state : std_logic_vector(3 downto 0);
    28. BEGIN
    30. -- Instantiate the Unit Under Test (UUT)
    31. utt : implementacio13 PORT MAP(
    32. rst => rst,
    33. clk => clk,
    34. a => a,
    35. b => b,
    36. state => state
    37. );
    39. stim_proc : process
    40. begin
    41. clk <= '1';
    42. rst <= '1';
    43. wait for 10 ns;
    44. clk <= '0';
    45. rst <= '1';
    46. wait for 10 ns;
    47. clk <= '1';
    48. wait for 10 ns
    49. clk <= '0';
    50. wait for 10 ns
    51. clk <= '1';
    52. wait for 10 ns
    53. clk <= '0';
    54. wait for 10 ns
    55. clk <= '1';
    56. rst <= '0';
    57. wait for 10 ns;
    58. clk <= '0';
    59. wait for 10 ns;
    60. clk <= '1';
    61. wait for 10 ns;
    62. clk <= '0';
    63. wait for 10 ns;
    64. clk <= '1';
    65. wait for 10 ns
    66. clk <= '0';
    67. wait for 10 ns;
    68. clk <= '1';
    69. wait for 10 ns
    70. clk <= '0';
    71. wait for 10 ns;
    72. clk <= '1';
    73. wait for 10 ns
    75. end process;
    77. END;


    SEGUNDA PARTE: Maquina de estado tipo MOORE

    Con el ejemplo anterior escribir y simular en VHDL el siguiente diagrama de estado.

    1. library IEEE;
    2. use IEEE.STD_LOGIC_1164.ALL;
    5. entity implementation is
    6. Port (
    7. RST : in std_logic;
    8. up_down : in std_logic;
    9. clk : in std_logic;
    10. Q0,Q1 : oue std_logic
    11. state: out std_logic_vector (1 downto 0)
    12. );
    13. end implementation;
    15. architecture behavior of implementation is
    17. SIGNAL pstate: std_logic_vector (1 downto 0);
    18. SIGNAL n_state : std_logic_vector (1 downto 0);
    19. begin
    20. process (RST, clk)
    21. begin
    22. if RST ='1' then
    23. pstate <= "00";
    24. elsif clk = '1' and clk'event then
    25. pstate <= n_state;
    26. end if;
    27. end process;
    29. n_state<= "01" when (pstate="00" and upd_down='1') else
    30. "11" when (pstate="01" and up_down='1') else
    31. "10" when (pstate="11" and up_down='1') else
    32. "10" when (pstate="00" and up_down='0') else
    33. "11" when (pstate="10" and up_down='0') else
    34. "01" when (pstate="11" and up_down='0') else
    35. "00";
    37. Q0 <= '0' when pstate="00" else
    38. '1' when pstate="01" else
    39. '0' when pstate="10" else
    40. '1';
    42. Q1 <= '0' when pstate="00" else
    43. '0' when pstate="01" else
    44. '1' when pstate="10" else
    45. '1';
    47. end behavior;

    1. LIBRARY ieee;
    2. use ieee.std_logic_1164.ALL;
    4. ENTITY simula IS
    5. END simula;
    7. ARCHITECTURE behavior OF simula IS
    9. COMPONENT implementacion
    10. PORT(
    11. RST : IN std_logic;
    12. up_down : IN std_logic;
    13. clk : IN std_logic;
    14. Q0 : OUT std_logic;
    15. Q1 : OUT std_logic;
    16. state : OUT std_logic_vector (1 downto 0)
    17. );
    18. END COMPONENT;
    20. --Inputs
    21. SIGNAL RST : std_logic := '0';
    22. SIGNAL up_down : std-logic := '0';
    23. SIGNAL clk : std_logic := '0';
    25. --Outputs
    26. SIGNAL Q0 : std_logic;
    27. SIGNAL Q1 : std_logic;
    28. SIGNAl state : std_logic_vector (1 downto 0);
    30. BEGIN
    32. uut : implementacion PORT MAP(
    33. RST => RST,
    34. up_down => up_down,
    35. clk => clk,
    36. Q0 => Q0,
    37. Q1 => Q1,
    38. state => state
    39. );
    41. stim_proc : process
    42. begin
    44. clk <= '1';
    45. RST <= '1';
    46. up_down <= '0';
    47. wait for 10 ns;
    48. clk <= '0';
    49. RST <= '1';
    50. wait for 10 ns;
    51. clk <= '1';
    53. wait for 10 ns;
    54. clk <= '0';
    55. wait for 10 ns
    56. clk <= '1';
    58. wait for 10 ns
    59. clk <= '0';
    60. wait for 10 ns;
    61. clk <='1';
    62. RST <= '0';
    63. up_down<='0'
    64. wait for 10 ns;
    65. clk <= '0';
    66. up_down <= '0';
    67. wait for 10 ns;
    68. clk <= '1';
    69. up_down <= '0';
    70. wait for 10 ns;
    71. clk <= '0';
    72. up_down <= '0';
    73. wait for 10 ns;
    74. clk <= '1';
    75. up_down <= '1';
    76. wait for 10 ns;
    77. clk <= '0';
    78. up_down <= '1';
    79. wait for 10 ns;
    80. clk <= '1';
    81. up_down <= '1';
    82. wait for 10 ns
    83. clk <= '0';
    84. up_down <= '1';
    85. wait dor 10 ns;
    86. end process;
    88. END;

    TERCERA PARTE: Maquina de estado tipo Mealy

    Con el primer ejemplo, codificar, escribir y simular en VHDL el siguiente diagrama de estado

    Le damos valores a las salidas ( codificamos)

    • S0 = 00
    • S1 = 01
    • S2 = 10
    • S3 = 11

    1. library IEEE;
    2. use IEEE.std_logic_1164.ALL;
    4. entity imple is
    5. Port ( y : in std_logic;
    6. rst : in std_logic;
    7. clk : in std_logic;
    8. z : in std_logic;
    9. Q0: out std_logic;
    10. Q1 : out std_logic;
    11. state : out std_logic_vector(1 downto 0));
    12. end imple;
    14. architecture behavioral of imple is
    16. signal pstate : std_logic_vector (1 downto 0);
    17. signal n_state : std_logic_vector (1 downto 0);
    18. begin
    19. process (rst, clk)
    20. begin
    21. if RST ='1' then
    22. pstate <= "00";
    23. elsif clk ='1' and clk'event then
    24. pstate <= n_state;
    25. end if;
    26. end process;
    28. state <= pstate;
    30. n_state <= "01" when (pstate="00" and y='1' and z='1') else
    31. "10" when (pstate="01" and y='1' and z='0') else
    32. "11" when (pstate="10" and y='1' and z='1') else
    33. "00" when (pstate="11" and y='1' and z='1') else
    34. pstate;
    36. Q0 <= '0' when pstat ="00" else
    37. '1' when pstat ="01" else
    38. '0' when pstat ="10" else
    39. '1';
    41. Q1 <= '0' when pstat ="00" else
    42. '0' when pstat ="01" else
    43. '1' when pstat ="10" else
    44. '1';
    46. end behavioral;

    1. LIBRARY ieee;
    2. use ieee.std_logic_1164.ALL;
    4. ENTITY simula IS
    5. END simula;
    7. ARCHITECTURE behavior OF simula IS
    9. COMPONENT imple
    10. PORT(
    11. rst : IN std_logic;
    12. y : IN std_logic;
    13. clk : IN std_logic;
    14. z : in std_logc;
    15. Q0 : OUT std_logic;
    16. Q1 : OUT std_logic;
    17. state : OUT std_logic_vector (1 downto 0)
    18. );
    19. END COMPONENT;
    21. --Inputs
    22. SIGNAL y : std_logic := '0';
    23. SIGNAL rst : std-logic := '0';
    24. SIGNAL clk : std_logic := '0';
    25. SIGNAL z : std_logic := '0';
    27. --Outputs
    28. SIGNAL Q0 : std_logic;
    29. SIGNAL Q1 : std_logic;
    30. SIGNAl state : std_logic_vector (1 downto 0);
    32. BEGIN
    34. uut : imple PORT MAP(
    35. y => y,
    36. rst => rst,
    37. clk => clk,
    38. z => z,
    39. Q0 => Q0,
    40. Q1 => Q1,
    41. state => state
    42. );
    44. stim_proc : process
    45. begin
    47. clk <= '1';
    48. rst <= '1';
    49. wait for 10 ns;
    50. clk <= '0';
    51. rst <= '1';
    52. wait for 10 ns;
    53. clk <= '1';
    55. wait for 10 ns;
    56. clk <= '0';
    57. wait for 10 ns
    58. clk <= '1';
    60. wait for 10 ns
    61. clk <= '0';
    62. wait for 10 ns;
    63. clk <='1';
    64. rst <= '0';
    65. y <='0'
    66. z <='0';
    67. wait for 10 ns;
    68. clk <= '0';
    69. y <= '1';
    70. z <= '1';
    71. wait for 10 ns;
    72. clk <= '1';
    73. y <= '0';
    74. z <= '1';
    75. wait for 10 ns;
    76. clk <= '0';
    77. y <= '1';
    78. z <= '0';
    79. wait for 10 ns;
    80. clk <= '1';
    81. y <= '0';
    82. z <= '0';
    83. wait for 10 ns;
    84. clk <= '0';
    85. y <= '1';
    86. z <= '1';
    87. wait for 10 ns;
    88. clk <= '1';
    89. y <= '0';
    90. z <= '0';
    91. wait for 10 ns
    92. y <= '1';
    93. z <= '1';
    94. wait dor 10 ns;
    95. end process;
    97. END;

    Aplicación de lo aprendido

    Realice el diseño de un contador ascendente/ descendente de 8 bits controlable mediante un bit para el cual en cero cuente descendentemente y en 1 ascendentemente. Usando contadores o máquina de estados.

    1. library IEEE;
    2. use IEEE.STD_LOGIC_1164.ALL;
    3. use IEEE.STD_LOGIC_ARITH.ALL
    4. use IEEE.STD_LOGIC_UNSIGNED.ALL
    5. use IEEE.NUMERIC_STD.ALL
    7. entity imple is
    8. port ( clk: in STD_LOGIC;
    9. conteo: in STD_LOGIC;
    10. salida: out STD_LOGIC_vector(7downto 0)
    11. );
    13. end imple;
    15. architecture behavioral od imple is
    16. SIGNAL cuenta: STD_LOGIC_VECTOR (7 downt 0) :="00000000";
    17. begin
    18. process (clk)
    19. begin
    20. if clk ='1' and clk'event then
    21. if conteo ='1' then
    22. cuenta <= cuenta +1;
    23. else
    24. cuenta <= cuenta - 1;
    25. end if;
    26. end if;
    27. end process;
    28. salida <= cuenta;
    30. end behavioral;

    1. LIBRARY ieee;
    2. USE ieee.std_logic_1164.ALL;
    4. ENTITY imple_TB is
    5. END imple_TB;
    7. ARCHITECTURE behavior OF imple_TB IS
    9. --Component Declaration for the Unit Under Test (UUT)
    11. COMPONENT imple
    12. PORT(
    13. clk : IN std_logic;
    14. conteo: IN std_logic;
    15. salida : OUT std_logic_vector(7 downto 0)
    16. );
    17. END COMPONENT;
    20. --Inputs
    21. signal clk : std_logic := '0';
    22. signal conteo : std_logic := '0';
    24. -- Outputs
    25. signal salida : std_logic_vecto (7 downto 0);
    27. BEGIN
    29. -- Instatiate the Unit Under Test (UUT)
    30. utt: imple PORT MAP (
    31. clk => clk,
    32. conteo => conteo,
    33. salida => salida
    34. );
    36. --Stimulus process
    37. stim_proc: process
    38. begin
    39. clk <= '0',
    40. conteo <= '1';
    41. wait for 10 ns;
    42. clk <= '1',
    43. conteo <= '1';
    44. wait for 10 ns;
    45. clk <= '0',
    46. conteo <= '1';
    47. wait for 10 ns;
    48. clk <= '1',
    49. conteo <= '1';
    50. wait for 10 ns;
    51. clk <= '0',
    52. conteo <= '1';
    53. wait for 10 ns;
    54. clk <= '1',
    55. conteo <= '1';
    56. wait for 10 ns;
    57. clk <= '0',
    58. conteo <= '1';
    59. wait for 10 ns;
    60. clk <= '1',
    61. conteo <= '1';
    62. wait for 10 ns;
    63. clk <= '0',
    64. conteo <= '1';
    65. wait for 10 ns;
    66. clk <= '1',
    67. conteo <= '1';
    68. wait for 10 ns;
    69. clk <= '0',
    70. conteo <= '1';
    71. wait for 10 ns;
    72. clk <= '1',
    73. conteo <= '1';
    74. wait for 10 ns;
    75. clk <= '0',
    76. conteo <= '1';
    77. wait for 10 ns;
    78. clk <= '1',
    79. conteo <= '1';
    80. wait for 10 ns;
    81. clk <= '0',
    82. conteo <= '1';
    83. wait for 10 ns;
    84. clk <= '1',
    85. conteo <= '1';
    86. wait for 10 ns;
    87. wait;
    88. end process;
    89. END;

    Pueden descargar los archivos de ISE desde el siguiente enlace:https://github.com/mokuzaru/vhdl_labs

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